This document relates generally to semiconductor devices, and more specifically to methods of forming insulated gate devices and structures.
Metal oxide field effect semiconductor transistor (MOSFET) devices are used in many power switching applications such as dc-dc converters. In a typical MOSFET, a gate electrode provides turn-on and turn-off control with the application of an appropriate gate voltage. By way of example, in an n-type enhancement mode MOSFET, turn-on occurs when a conductive n-type inversion layer (i.e., channel region) is formed in a p-type body region in response to the application of a positive gate voltage, which exceeds an inherent threshold voltage. The inversion layer connects n-type source regions to n-type drain regions and allows for majority carrier conduction between these regions.
There is a class of MOSFET devices in which the gate electrode is formed in a trench that extends downward from a major surface of a semiconductor material, such as silicon. Current flow in this class of devices is primarily vertical, and, as a result, device cells can be more densely packed. All else being equal, the more densely packed device cells increases the current carrying capability and reduces on-resistance of the device.
Achieving the lowest specific on-resistance (ohm-area), which is an important goal of MOSFET device designers, can determine product cost and gross margins or profitability. In particular, the low specific on-resistance allows for a smaller MOSFET die or chip, which in turn leads to lower costs in semiconductor materials and package structures. However, challenges continue to exist in designing and manufacturing high density MOSFET devices that achieve lower specific on-resistance, that have optimum switching performance, that support voltage scaling (i.e., support a range of drain-to-source breakdown voltage (BVdss) requirements), and that are cost effective to manufacture.
Accordingly, methods and structures are needed for semiconductor devices that have lower specific on-resistance and optimum switching performance, that support voltage scaling, and that are cost effective to manufacture.
For simplicity and clarity of illustration, elements in the figures are not necessarily drawn to scale, and the same reference numbers in different figures denote generally the same elements. Additionally, descriptions and details of well-known steps and elements may be omitted for simplicity of the description. As used herein current-carrying electrode means an element of a device that carries current through the device, such as a source or a drain of an MOS transistor, an emitter or a collector of a bipolar transistor, or a cathode or anode of a diode, and a control electrode means an element of the device that controls current through the device, such as a gate of a MOS transistor or a base of a bipolar transistor. Although the devices are explained herein as certain N-channel devices, a person of ordinary skill in the art understands that P-channel devices and complementary devices are also possible in accordance with the present description. For clarity of the drawings, doped regions of device structures are illustrated as having generally straight-line edges and precise angular corners; however, those skilled in the art understand that due to the diffusion and activation of dopants, the edges of doped regions are generally not straight lines and the corners are not precise angles.
Furthermore, the term “major surface” when used in conjunction with a semiconductor region or substrate means the surface of the semiconductor region or substrate that forms an interface with another material, such as a dielectric, an insulator, a conductor, or a polycrystalline semiconductor. The major surface can have a topography that changes in the x, y and z directions.
In addition, structures of the present description may embody either a cellular base design (in which the body regions are a plurality of distinct and separate cellular or stripe regions) or a single base design (in which the body region is a single region formed in an elongated pattern, typically in a serpentine pattern or a central portion with connected appendages). However, one embodiment of the present description will be described as a cellular base design throughout the description for ease of understanding. It should be understood that the present disclosure encompasses both a cellular base design and a single base design.